1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device having a spare memory cell for replacement of a defective memory cell in which data is electrically rewritable.
2. Description of the Background Art
FIG. 8 is a block diagram showing a structure of a conventional synchronous dynamic random access memory (hereinafter referred to as SDRAM), and FIG. 9 is a circuit block diagram showing a structure of its main portion. Referring to FIGS. 8 and 9, the SDRAM includes a clock buffer 51, a control signal buffer 52, an address buffer 53, a mode register 54, and a control circuit 55.
Clock buffer 51 is activated by signal CKE and transmits external clock signal CLK to control signal buffer 52, address buffer 53 and control circuit 55. Control signal buffer 52 transmits external control signals /CS, /RAS, /CAS, /WE and DQM to control circuit 55 synchronously with external clock signal CLK from clock buffer 51. Address buffer 53 transmits external address signals A0-A10 as well as bank selection signal BA to control circuit 55 synchronously with external clock signal CLK from clock buffer 51. Mode register 54 stores a mode designated by external address signals A0-A10 or the like. Control circuit 55 generates various internal signals according to signals supplied from buffers 51-53 and mode register 54, and controls the entire SDRAM.
The SDRAM further includes a memory array 56a (bank #0), a memory array 56b (bank #1), redundant memory arrays (RMA) 57a and 57b, sense refresh amplifier and input/output control circuits 58a and 58b, row decoders 59a and 59b, column decoders 60a and 60b, redundant column decoders 61a and 61b, and an input/output buffer 62.
As shown in FIG. 9, memory array 56a includes a plurality of memory cells MC arranged in rows and columns, a word line WL provided corresponding to each row, and a bit line pair BL and /BL provided corresponding to each column. Memory array 56a includes, for example, 1024 word lines WL, and 256 bit line pairs BL and /BL.
Memory cell MC is of a well-known type including a transistor for access and a capacitor for storing information. Word line WL transmits an output from row decoder 59a and activates memory cell MC in a selected row. A data signal is input from bit line pair BL and /BL to a selected memory cell MC or output from a selected memory cell MC to bit line pair BL and /BL.
Redundant memory array 57a has the same structure as memory array 56a except that redundant memory array 57a has a smaller number of columns than memory array 56a. Memory array 56a and redundant memory array 57a have the same number of rows, and word line WL is shared between memory array 56a and redundant memory array 57a. Now suppose that redundant memory array 57a has N+1 (N is an integer of 0 or more) columns. If there exists a defective column in memory array 56a, the column is replaced with a column in redundant memory array 57a.
Sense refresh amplifier and input/output control circuit 58a includes: a data signal input/output line pair IO and /IO (IOP); a column selection line CSL provided corresponding to each column in memory array 56a; a spare column selection line SCSL provided corresponding to each column in redundant memory array 57a; a column selection gate 63; a sense refresh amplifier 64; and an equalizer 65 provided corresponding to each column respectively. Column selection gate 63 includes a pair of N channel MOS transistors connected between bit line pair BL and /BL and data signal input/output line pair IO and /IO of a corresponding column. The gate of each N channel MOS transistor is connected to column decoder 60a or redundant column decoder 61a via column selection line CSL or spare column selection line SCSL of a corresponding column. When column selection line CSL or spare column selection line SCSL is caused to become H level of a selected level by column decoder 60a or redundant column decoder 61a, N channel MOS transistor is turned on, and bit line pair BL and /BL and data signal input/output line pair IO and /IO are coupled.
When sense amplifier activation signals SE and /SE respectively become H level and L level, sense refresh amplifier 64 amplifies a slight potential difference between bit line pair BL and BL to supply voltage Vcc. When bit line equalize signal BLEQ attains H level of an activation level, equalizer 65 equalizes the potential on bit lines BL and /BL to bit line potential VBL.
Row decoder 59a causes one of the 1024 word lines WL to become H level of the selected level according to predecode signals X0-X23 from control circuit 55. Column decoder 60a causes one of the 256 column selection lines CSL to become H level of the selected level according to predecode signals Y0-Y19 from control circuit 55. Redundant column decoder 61a causes one of the N+1 spare column selection lines SCSL to attain H level of the selected level according to predecode signals Z0-ZN from control circuit 55.
Memory arrays 56a and 56b, redundant memory arrays 57a and 57b, sense refresh amplifier and input/output control circuits 58a and 58b, row decoders 59a and 59b, column decoders 60a and 60b, and redundant column decoders 61a and 61b have the same structure respectively.
One end of data signal input/output line pair IOP is, as shown in FIG. 8, connected to input/output buffer 62. In the write mode, input/output buffer 62 applies externally supplied data to a selected memory cell MC via data signal input/output line pair IOP. In the read mode, input/output buffer 62 outputs data read from a selected memory cell MC to the outside.
Next an operation of the SDRAM shown in FIGS. 8 and 9 is briefly described. In the write mode, a column decoder (in this case 60a or 61a) corresponding to a selected bank (e.g. #0) sets column selection line CSL or SCSL according to predecode signals Y0-Y19 or Z0-ZN to H level of the activation level, and causes column selection gate 63 to be conductive.
Input/output buffer 62 applies externally supplied write data to bit line pair BL and /BL in a selected column via data signal input/output line pair IO and /IO. Write data is supplied as the potential difference between bit line pair BL and /BL. Next row decoder 59a sets a word line WL in a row according to predecode signals X0-X23 to H level of the selected level, and activates memory cell MC in the row. The capacitor of the selected memory cell MC stores electric charge with its amount corresponding to the potential of bit line BL or /BL.
In the read mode, bit line equalize signal BLEQ falls to L level of an inactivation level, equalizer 65 is inactivated, and equalization of bit lines BL and /BL is stopped. Row decoder 59a sets word line WL in a row according to predecode signals X0-X23 to H level of the selected level. The potential of bit lines BL and /BL slightly changes according to the amount of potential of the capacitor in the activated memory cell MC.
Next sense amplifier activation signals SE and /SE respectively attain H level and L level and sense refresh amplifier 64 is activated. When the potential of bit line BL is slightly higher than that of bit line /BL, the potential of bit line BL is increased to H level, and the potential of bit line /BL is decreased to L level. On the other hand, when the potential of bit line /BL is slightly higher than that of bit line BL, the potential of bit line /BL is increased to H level and the potential of bit line BL is decreased to L level.
Column decoder 60a or 61a sets column select line CSL or SCSL in a column according to predecode signals Y0-Y19 or Z0-ZN to H level of the selected level, and causes column selection gate 63 in the column to be conducting. Data on bit line pair BL and /BL in the selected column is supplied to input/output buffer 62 via column selection gate 63 and data signal input/output line pair IO and /IO. Input/output buffer 62 outputs read data to the outside.
Next a method of selecting column in the SDRAM is described in detail.
256 column selection lines CSL0-CSL255 in memory array 56a are divided in advance into 8 blocks each including 32 column selection lines CSL, and each block is divided into 8 groups each including 4 column selection lines CSL in advance. Predecode signals Y12-Y19 are respectively allocated to eight blocks, predecode signals, Y4-Y11 are respectively allocated to eight groups and predecode signals Y0-Y3 are respectively allocated to four column selection lines CSL. Accordingly, one of the predecode signals Y12-Y19, signal Yk (k is an integer of 12-19), one of the predecode signals Y4-Y12, signal Yj (j is an integer of 4-12), and one of the predecode signals Y0-Y3, signal Yi (i is an integer of 0-3) designate one of the 256 column selection lines CSL0-CSL255, CSLm (m is an integer of 0-255).
Specifically, first control circuit 55 takes address signals A0-A7 as column address signals CA0-CA7 according to signals supplied from buffers 51 and 52, and converts the signals CA0-CA7 to complementary address signals CAD0-CAD7 and /CAD0-/CAD7.
As shown in FIGS. 10A-10C, control circuit 55 is provided with eight predecoders 70, eight predecoders 75, and four predecoders 80. Eight predecoders 70 are respectively provided corresponding to predecode signals Y12-Y19. Eight predecoders 75 are respectively provided corresponding to predecode signals Y4-Y11. 4 predecoders 80 are provided corresponding to predecode signals Y0-Y3 respectively.
Any three of complementary column address signals CAD5-CAD7 and /CAD5-/CAD7 are allocated to each of predecode signals Y12-Y19 in advance. Each predecoder 70 includes NAND gates 71 and 73 and inverters 72 and 74. NAND gate 71 receives three complementary column address signals allocated in advance, and its output is supplied to inverter 72. NAND gate 73 receives an output from inverter 72 and signal ISCE, and its output is supplied to the input of inverter 74. An output from inverter 74 is predecode signal Yk. Predecoder 70 outputs H level when all of the allocated three complementary column address signals and signal /SCE attain H level.
Any three of complementary column address signals CAD2-CAD4 and /CAD2-/CAD4 are allocated to each of predecode signals Y4-Y11 in advance. Each predecoder 75 includes NAND gates 76 and 78 and inverters 77 and 79. NAND gate 76 receives the three complementary column address signals that have been allocated in advance, and its output is supplied to inverter 77. NAND gate 78 receives an output from inverter 77 and signal CDE, and its output is applied to inverter 79. An output from inverter 79 is predecode signal Yj. Predecoder 75 outputs H level when the allocated three complementary column address signals and signal CDE all attain H level.
Any two of complementary column address signals CAD0, CAD1, /CAD0 and /CAD1 are allocated to each of predecode signals Y0-Y3 in advance. Each predecoder 80 includes NAND gates 81 and 83 and inverters 82 and 84. NAND gate 81 receives the two complementary column address signals which have been allocated in advance, and its output is input to inverter 82. NAND gate 83 receives an output from inverter 82 and signal CDE, and its output is input to inverter 84. An output from inverter 84 is predecode signal Yi. Predecoder 80 outputs H level when the two complementary column address signals allocated and signal CDE all attain H level.
As shown in FIG. 11, column decoder 60a includes 256 column decoder unit circuits 85. The 256 column decoder unit circuits 85 are provided corresponding to 256 column selection lines CSL0-CSL255 respectively. To each of column selection lines CSL0-CSL255, any one of predecode signals Y12-Y19, yk, any one of predecode signals Y4-Y11, Yj, and any one of predecode signals Y0-Y3, Yi are allocated in advance.
Column decoder unit circuit 85 includes an NAND gate 86 and an inverter 87. NAND gate 86 receives the three predecode signals Yi, Yj, and Yk which have been allocated in advance, and its output node is connected to a corresponding column selection line CSLm via inverter 87. Column decoder unit circuit 85 sets the corresponding column selection line CSLm to H level of the selected level when the three predecode signals Yi, Yj and Yk which have been allocated all attain H level.
If there is a defective column in memory array 56a, the address of the defective column is stored in control circuit 55. When the address is supplied to control circuit 55, control circuit 55 outputs predecode signal Zn (n is an integer of 0-N) instead of predecode signals Yi, Yj and Yk, and selects spare column selection line SCSLn instead of defective column selection line CSL.
Referring to FIGS. 12 and 13, N+1 program circuits 90 are provided in control circuit 55. N+1 program circuits 90 are provided corresponding to predecode signals Z0-ZN, respectively.
Each program circuit 90 includes fuses 92, 110a-117a and 110b-117b, P channel MOS transistors 91 and 120-127, an N channel MOS transistor 93, NAND gates 94, 134 and 138, inverters 95, 135-137 and 139, switching inverters 100a-107a and 100b-107b, and NOR gates 130-133.
P channel MOS transistor 91, fuse 92 and N channel MOS transistor 93 are connected in series between the line of supply potential Vcc and the line of ground potential GND. The gates of P channel MOS transistor 91 and N channel MOS transistor 93 receive precharge signal /PC. Precharge signal /PC falls to L level when read command or write command is supplied at the rising of clock signal CLK, and rises to H level when clock signal CLK next falls. Fuse 92 is blown when a corresponding spare column selection line SCSL is used, and not blown if a corresponding spare column selection line SCSL is not used.
When fuse 92 is blown, the drain (node N91) of P channel MOS transistor is charged to H level via P channel MOS transistor 91 when precharge signal /PC falls to L level. Node N91 is not discharged even if precharge signal /PC attains H level, maintaining H level. If fuse 92 is not blown, P channel MOS transistor 91, fuse 92 and N channel transistor 93 constitute an inverter. Accordingly, node N91 outputs an inverted signal of precharge signal /PC.
NAND gate 94 receives a signal on node N91 and precharge signal /PC, and its output is supplied to switching inverters 100a-107a and 100b-107b and the gates of P channel MOS transistors 120-127 via inverter 95.
If fuse 92 is blown, precharge signal /PC is delayed in NAND gate 94 and inverter 95 to become output signal .phi.95 from inverter 95. If fuse 92 is not blown, output signal .phi.95 is always at L level.
Switching inverters 100a-107a and 100b-107b are provided corresponding to complementary column address signals /CAD0-/CAD7 and CAD0-CAD7, respectively. As shown in FIG. 15, switching inverter 100a includes a P channel MOS transistor 141 and N channel MOS transistors 142 and 143 connected in series between the line of supply potential Vcc and the line of ground potential GND. The gates of MOS transistors 141 and 143 receive corresponding complementary column address signal /CAD0, and the gate of N channel MOS transistor 142 receives signal .phi.95. The drain of P channel MOS transistor 141 is an output node N141 of switching inverter 100a.
When signal .phi.95 is at H level, N channel MOS transistor 142 is turned on and switching inverter 100a is activated. When signal .phi.95 is at L level, N channel MOS transistor 142 is turned off and switching inverter 100a is inactivated. The operations of other switching inverters 101a-107a and 100b-107b are similar to that of switching inverter 100a.
Fuses 110a-117a and 110b-117b are provided corresponding to complementary column address signals /CAD0-/CAD7 and CAD0-CAD7 respectively. Fuses 110a-117a are connected between output nodes N141 of corresponding switching inverters 100a-107a and nodes N120-N127. Fuses 110b-117b are connected between output nodes N141 of corresponding switching inverters 100b-107b and nodes N120-N127.
A fuse corresponding to a complementary column address signal designating a defective column selection line CSL is not blown, and other fuses are blown and the address of the defective column selection line CSL is stored. When the address is input, the outputs from switching inverters 100a-107a and 100b-107b are transmitted to nodes N120-N127 via fuses 110a-117a and 110b-117b.
P channel MOS transistors 120-127 are connected between the line of supply potential Vcc and nodes N120-N127 respectively, and their gates receive signal .phi.95. When signal .phi.95 falls to L level, P channel MOS transistors 120-127 are turned on, and nodes N120-N127 are precharged to H level.
NOR gate 130 receives signals that are present on nodes N120 and N121. NOR gate 131 receives signals present on nodes N122 and N123. NOR gate 132 receives signals present on nodes N124 and N125. NOR gate 133 receives signals on nodes N126 and N127. NAND gate 134 receives outputs from NOR gates 130-133.
As shown in FIG. 13, output signal .phi.134 from NAND gate 134 is amplified by inverters 135 and 136 to become signal /SCE, and supplied to inverter 137. NAND gate 138 receives an output from inverter 137 and signal CDE. An output from NAND gate 138 is inverted by inverter 139 to become predecode signal Zn.
Accordingly, program circuit 90 sets signal /SCE to L level when a complementary column address signal which is programmed by fuses 92, 110a-117a and 110b-117b is supplied. When signal CDE attains H level, program circuit 90 sets corresponding predecode signal Zn to H level.
Referring to FIG. 16, redundant column decoder 61a includes N+1 redundant column decoder unit circuits 144. N+1 redundant column decoder unit circuits 144 are provided corresponding to N+1 spare column selection lines SCSL0-SCSLN respectively. Predecode signals Z0-ZN are allocated to spare column selection lines SCSL0-SCSLN respectively in advance.
Each redundant column decoder unit circuit 144 includes inverters 145 and 146 connected in series. When the allocated predecode signal Zn rises to H level, redundant column decode unit circuit 144 sets corresponding spare column selection line SCSLn to H level of the selected level.
FIGS. 17A-17D are timing charts showing a column selecting operation of the SDRAM. With reference to FIGS. 17A-17D, at time t1, complementary column address signals /CAD0-/CAD7 and CAD0-CAD7 are defined.
If complementary column address signals /CAD0-/CAD7 and CAD0-CAD7 are programmed by program circuit 90, signal /SCE falls to L level and signal CDE rises to H level at time t2 after a prescribed time (delay time of program circuit 90) has passed from time t1. Responsively, an output from predecoder 70 in FIG. 10, that is, predecode signal Yk is fixed at H level, and an output from column decoder unit circuit 85 in FIG. 11, that is, column selection line CSLm is fixed at L level. At the same time, predecode signal Zn shown in FIG. 13 rises to H level, an output from redundant column decoder unit circuit 144 shown in FIG. 16, that is, spare column selection line SCSLn rises to H level.
If complementary column address signals /CAD0-/CAD7 and CAD0-CAD7 are not programmed by program circuit 90, signal /SCE does not change to maintain H level, and signal CDE attains H level at time t2. Responsively, one of predecode signals Y12-Y19 shown in FIG. 10, that is, signal Yk, one of predecode signals Y4-Y11, Yj, one of predecode signals Y0-Y3, Yi attain H level, and an output from one of the 256 column decoder unit circuits 85 shown in FIG. 11, that is, column selection line CSLm rises to H level of the selected level. On the other hand, predecode signal Zn shown in FIG. 13 is fixed at L level, and an output from redundant decoder unit circuit 144 in FIG. 16, that is, spare column selection line SCSLn is fixed at L level of the non-selected level.
The access to column selection lines CSL and SCSL is not carried out until time t2 since if the access to column selection lines CSL and SCSL is started at time t1, a defective column selection line CSLm is selected between times t1 and t2, and a spare column selection line SCSLn is selected after time t2, resulting in the multi-selection.
In the normal DRAM, although predecoding is started after an address transition detecting circuit detects transition of a complementary address signal, the multi-selection does not occur because of a sufficiently long delay time of the address transition detecting circuit.
However, in the conventional SDRAM, the access to column selection line CSL is not carried out until signal /SCE is defined even if there is no defective column and spare column selection line SCSL is not used. As a result, there exists a useless waiting time.